Architecture for serializer/deserializer (SerDes) receiver data path processing generally combines a front-end continuous-time linear equalizer (CTLE) and a decision feedback equalizer (DFE). These equalizing components are automatically adjusted using adaptive algorithms, e.g., least mean squares (LMS). For high-speed applications, data path equalization components are most often implemented as analog, transistor-level circuits while the adaptation is implemented via digital blocks.
An alternative method is to implement only an analog to digital converter (ADC) as an analog circuit, processing the received signal fully in the digital domain. A digital signal processing (DSP) data path of this nature offers technical potential for advanced DSP algorithms, expanding applications to extra long reach (XLR) channels or modulation schemes higher than non-return to zero (e.g., PAM-4). A digital receiver additionally has better reliability, testability and flexibility compared to its analog counterparts, and is easier to port across technology nodes.
There are at least two major technical challenges associated with building a DSP SerDes receiver: first, the technical feasibility of a high-speed, low-power ADC for digitizing a received analog signal, and second, lower clock speeds in the digital domain as opposed to analog alternatives. The former can be addressed by contemporary ADC architectures. The latter requires parallelization of hardware, which in turn creates its own set of challenges. It may be desirable to provide a primarily or fully digital SerDes receiver that provides high speed performance while minimizing the necessary area.